1. Field of the Invention
The invention relates to a circuit arrangement for the read and/or write access to storage cells of a semiconductor memory.
2. Description of the Prior Art
In the field of electronic data processing systems there has, in recent years, been an almost soaring development towards systems of increasing performance. An important contribution has been the rapid development of the integrated circuit technology. In that technology particularly effective memories could be made which are required in all modern computer systems for the storage of data, programs, intermediate results, etc. It is particularly in this field that the integrated semiconductor memories are increasingly used in view of their unique flexibility and adaptability with regard to memory size, organization, speed, etc. to the respective conditions.
A general aim for such a memory system is that it should be as low-priced, quick, and reliable as possible. For the individual memory components, the memory chips, there result among other things the following main demands. A maximum of storage cells should be provided on a chip. The power dissipation per chip should be as low as possible. Reading and writing of the stored information should be realizable as quickly as possible. However, it is known that these demands are partly or fully contradictory so that a memory chip design will always aim at finding a relative optimum for a specific application with given technological conditions.
Particularly advantageous from the packing density and power dissipation points of view are dynamic semiconductor storge concepts. There, the information is stored in the form of a capacitive charge condition. Compared with static storage cells, dynamic storage cells can be made with less switching elements. Known dynamic storage cells include the so-called one-device cells, two-device cells, etc. which are at present mostly made in MOS technology. A known two-FET storage cell is described in the publication in the IBM Technical Disclosure Bulletin, Vol. 18, No. 3, August 1975, pp. 786/787. It is, however, known that dynamic storage cells can also be made in bipolar technology.
However, the development of storage cells which continuously decrease in size, for packing reasons, involves the difficulty of reliably evaluating the extremely small storage signals of a storage cell which are coupled to the access lines. In the course of obtaining storage readout of maximum sensitivity, the effort and complexity involved in designing sensing circuits increases. Each write/read access, to give an example, demands a precisely fixed succession of several control signals having very close tolerances with respect to time. Depending on whether a read or a write access is made different control signal sequences have to be additionally provided. This has, however, the consequence that the performance of the resulting storage arrangement as a whole increasingly depends on the peripheral support circuits of the storage cell array normally provided on the memory semiconductor chip, i.e. particularly on the access circuits.
Other known prior art includes U.S. Pat. No. 3,806,898 to Askin and assigned to the assignee of the instant invention. Askin describes a dynamic single FET/capacitor memory cell array including an isolation device coupled between an array column or data line and a column decoder. The gate of the isolation device is maintained at a constant bias at an intermediate potential VL of approximately one FET threshold voltage drop above ground potential. The data lines are precharged to VL prior to the accessing of data and the setting of a dynamic latch. As described, the memory system includes two timing response disadvantages. First, since the data line precharge potential is low, speed and sensitivity of the sense latch is not optimized. Second, since the bias on the gate of the isolation device is also low, no current can be coupled through the column decoders until the sense latch is substantially fully set. This last limitation also compromises the speed of sensing data at the memory chip output pads.
U.S. Pat. No. 3,771,147 to Boll et al is also of interest as it relates to a dynamic single FET/capacitor memory cell array including dynamic sense latches in which column or data line switches are prebiased to be responsive to a differential sense signal developed by the sense latch. In this reference, all data line switches have their gate electrodes biased at one threshold voltage drop below the precharge potential, corresponding to a high FET logic level, provided on the data lines. When address signals are developed on the memory chip all but one of the column select lines are discharged to a low level logic potential. In order to prevent the data line switches from being conductive prior to the setting of the sense latch, the data input/output terminals coupled to the data line switches are biased at the same potential as the data lines. Although such a system avoids the problem presented by Askin of low level bit line precharging, it demands considerably more power dissipation as the column select lines must all be initially precharged. In addition, due to the relatively high precharge potential on the column select lines, requiring a high level of precharge on the input/output terminals, causes difficulty in rendering the circuit compatible with known bipolar current sensing circuits. Also since the precharge potential of the column select lines is at a relatively high level, being only one threshold voltage drop below the FET high level logic signal, the column switches begin to pass current to the sense latch at an early point in time thus possibly slowing down the response of the latch due to additional capacitive coupling added by rendering the column switch conductive when the column line reaches one threshold below the column select line precharge potential.